/**
 * project: 12_v02_Mic
 * try i2s fetch from micArray 
 * 2022.04.04 h.zheng 
 * copy from 12_Mic, change MIC_CK
 */


module mic
	(
		input wire CLK_IN,	
        input wire RST_N,
		output wire LED1,        
        input wire RXD,        
        output wire TXD,
		output wire LED_CK,
		output wire LED_DA,
		output wire MIC_WS,
		output wire MIC_CK,
		input wire MIC_D2
	);
		
    wire clk_192MHz;		
//    wire clk_3072kHz;
    wire clk_6144kHz;
    PLL mPLL (.refclk(CLK_IN),
		.reset(~RST_N),
		.clk0_out(clk_192MHz),
		.clk1_out(clk_6144kHz)		
    );	
	

	reg [25:0] count;
     
	
	initial
	begin
		count=26'b0;
	end
	
	always @(posedge clk_6144kHz or negedge RST_N) begin
        if (~RST_N)	
          count <= 0;        
        else
		  count <= count + 1'b1;	
	end
			
	wire MIC_CK_N = count[0]; //3072kHz
	wire MIC_WS_N = count[6]; //3072kHz/64

/*

	always @(posedge CLK_IN or negedge RST_N) begin
        if (~RST_N)	
          count <= 0;        
        else
		  count <= count + 1'b1;	
	end
			
	wire MIC_CK_N = count[2]; //3MHz
	wire MIC_WS_N = count[8]; //3MHz/64
*/    
  		

	
	assign MIC_CK = ~MIC_CK_N;
	assign MIC_WS = ~MIC_WS_N;
	
	reg [63:0] shift_reg;

	always @(posedge MIC_CK) begin
	    shift_reg <= {shift_reg[62:0], MIC_D2};	
	end	
		
	reg [63:0] data_reg;
	always  @(negedge MIC_WS) begin
        data_reg <= shift_reg;
	end		
	
    wire[23:0] data_l = data_reg[62:39];	
    wire[23:0] data_r = data_reg[30:7];	    

    //assume that it's signed data    
    wire[22:0] l_amplitude = data_l[23] ? ((~data_l[22:0])+1) : data_l[22:0];
    wire loud_voice = (l_amplitude[22:16]>=7'h07) ? 1'b1 : 1'b0;    

    assign LED1 = ~loud_voice;
//    assign LED1 = count[22];

    assign LED_CK = 1'b0;    
    assign LED_DA = 1'b0;    
	
		
    //uart module		
    
    wire tx_pulse;
    //tx period: 1/48k
//	assign tx_pulse = (count[8:0] == 9'h08) ? 1'b1 : 1'b0; //8 24MHz clock after negedge MIC_WS
    //tx period: 1/48k
//	wire tx_enable = (count[5:0] == 6'b100001) ? 1'b1 : 1'b0; //1 3072kHz clock after negedge MIC_WS
	wire tx_enable = (count[6:0] == 7'b1000001) ? 1'b1 : 1'b0; //1 3072kHz clock after negedge MIC_WS
	
//generate a tx pulse which is one period width of the driving clk of UART_TX	
	wire uart_clk = CLK_IN;    
	
    reg [1:0] one_pulse_cnt;
    reg one_pulse_cnt_en;	
    wire one_pulse_cnt_top;	
	always @(posedge tx_enable or posedge one_pulse_cnt_top) begin
        if (one_pulse_cnt_top)	
          one_pulse_cnt_en <= 1'b0;        
        else
		  one_pulse_cnt_en <= 1'b1;	
	end		  
    assign one_pulse_cnt_top = (one_pulse_cnt == 2'b11) ? 1'b1 : 1'b0;	
    wire one_pulse_cnt_clk = one_pulse_cnt_en & uart_clk;    
	always @(posedge one_pulse_cnt_clk or negedge one_pulse_cnt_en) begin
        if (~one_pulse_cnt_en)	
          one_pulse_cnt <= 0;        
        else
		  one_pulse_cnt <= one_pulse_cnt + 1'b1;	
	end
	assign tx_pulse = (one_pulse_cnt == 2'b10) ? 1'b1 : 1'b0;

    wire [7:0] SBUF_in; 	
    
//baudrate: 1000000    
//baud_rate_period_m1 = CLK_IN / 1M = 24M/1M = 24
//STABLE_TIME = baud_rate_period_m1/2 = 12

    UART_TX #(.STABLE_TIME(12), .BAUD_PERIOD_BITS(8)) UART_TX_i (
            .clk        (uart_clk),
            .reset_n    (RST_N),
            .sync_reset (~RST_N),
            
            .start_TX (tx_pulse),
            .baud_rate_period_m1 (8'd24),
//            .SBUF_in (8'b01000010),
            .SBUF_in (SBUF_in),
            .TXD (TXD));
            
    assign SBUF_in = data_l[23:16];



endmodule
